1. Field of the Invention
The present invention is in the field of digital television-signal-processing circuits, and, more particularly, is directed to the generation of sampling clocks for such circuits.
2. Description of the Related
In digital television-signal-processing circuits, there are basically three different possibilities of implementing the sampling system:
a) In a line-locked system, the sampled pixels of all picture lines, referred to the screen, are arranged one below the other along exactly vertical lines.
b) In a color-carrier-locked system, such as the system locked to four times the color-subcarrier frequency, the sampled pixels are generally located one below the other only approximately. As is well known, this is a consequence of the nonintegral interleaving relationship between color-subcarrier frequency and horizontal frequency and the 25-Hz frequency offset in the PAL color-television standard.
c) A further possible sampling system is constituted by the asynchronous clock, which is locked neither to the line nor to the color carrier.
Digitization and reconversion are commonly effected at the same clock rate, but under certain circumstances, e.g., in various flicker-reduction techniques, also at clock rates differing by a factor of 2 or 4.
Image enhancement techniques (e.g., techniques involving multi-dimensional filter algorithms) require that the video signals to be processed are sampled orthogonally. This means that the sample values of different lines or pictures, referred to the screen, must be arranged one below the other along exactly vertical lines. In system a), this requirement is satisfied by the sampling. In systems b) and c), an interpolation of the video signals must be performed which corrects the data for an orthogonal sampling pattern. This is done with a skew filter. The parameter of the data interpolation is the phase difference between an imaginary line-locked sampling clock and the actual sampling clock. The phase difference is determined digitally in a first phase-locked loop and delivered as a skew value.
If digitization and reconversion are effected at the same sampling rate, the orthogonal structure of the video data must be reversed after the filtering by mathematically restoring the data to their original phase position by a reciprocal skew operation.
In both analog and digital television-signal-processing circuits, horizontal synchronization is accomplished with two phase-locked loops (PLL 1 and PLL 2). The first phase-locked loop PLL 1 generates a horizontal reference clock hr which has exactly the same line frequency as the composite color signal to be processed, but not the phase jitter of this signal. During video recorder operation, phase variations of up to 2.times.10.sup.-6 sec may occur. The function of the second phase-locked loop PLL 2 is to maintain the exact position of the luminous spot on the tube, regardless of, for example, changes in component characteristics, line voltage, or temperature. The horizontal output stage is designed as a resonant circuit which responds to interference with hunting.
The commonly used methods to compensate for phase errors of the composite color signal via a phase shifter in the second phase-locked loop PLL 2 have the disadvantage that this control generates a spurious signal there and may cause hunting or overshoot.
This poses the problem that, on the one hand, phase changes of the video-signal source, particularly in the video recorder, must be transferred as quickly as possible to the deflection circuitry in order to adapt the horizontal output stage to the new phase. This requires a close coupling of the two phase-locked loops PLL 1 and PLL 2. On the other hand, noise components of the video-signal source are to be suppressed as far as possible, which would be supported by a loose coupling of the horizontal output stage to the instantaneous phase of the sync pulse.